Project Settings
Project Name CoreTSE_Webserver_syn Implementation Name synthesis
Top Module CoreTSE_Webserver Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 173 407 0 - 0m:10s - 11/17/2016
3:26:44 PM
(premap)Complete 62 16 0 0m:02s 0m:02s 190MB 11/17/2016
3:26:49 PM
(fpga_mapper)Complete 205 97 0 01m:04s 01m:04s 327MB 11/17/2016
3:27:54 PM
Multi-srs Generator Complete0m:02s11/17/2016
3:26:46 PM

Area Summary
Carry Cells 1456 Sequential Cells 5172
DSP Blocks (MACC) (dsp_used) 0 I/O Cells 23
Global Clock Buffers 27 Block Rams (RAM1K18) (v_ram) 14
LUTs (total_luts) 9782

Timing Summary
Clock NameReq FreqEst FreqSlack
CLK1_PAD50.0 MHzNANA
CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB12.5 MHz107.9 MHz35.365
FCCC_0/GL050.0 MHz35.8 MHz-1.275
FCCC_1/GL062.5 MHz65.8 MHz2.685
FCCC_1/GL162.5 MHz80.2 MHz7.106
FCCC_2/GL0125.0 MHz160.4 MHz2.738
FCCC_3/GL0125.0 MHzNANA
FCCC_3/GL1125.0 MHz89.5 MHz-1.587
OSC_0/I_RCOSC_25_50MHZ/CLKOUT50.0 MHz431.2 MHz17.681
SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]125.0 MHzNANA
SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]125.0 MHzNANA
pemgt|CORETSE_AHBi01_inferred_clock100.0 MHz152.0 MHz3.420
System100.0 MHz477.6 MHz7.906

Optimizations Summary
Combined Clock Conversion 8 / 1